The present invention relates to a synchronous counter counting cycles of an input clock having a fixed period. More particularly, the present invention relates to a synchronous counter capable of reducing carry propagation delay in a multi-stage counter. The present invention also relates to a method of reducing carry propagating delay for a synchronous counter used in a multi-stage counter.
The synchronous counter is a well known circuit element. Conventional synchronous counters perform up or down count operations using a plurality of flip-flops which respond to a clock having a fixed period. Synchronous counters are generally used in a variety of integrated circuits, but are particularly important components in semiconductor memory devices which access stored data according to an incrementing or decrementing address signal.
In other applications, a first synchronous counter, typically having a simple structure, within a first circuit stage provides an output signal to a subsequent circuit stage in response to transitions in a synchronous clock. In such applications, the stability and efficiency of conventional counters is improved by using the carry signal generated by the first synchronous counter in the first circuit stage as the output signal to the subsequent circuit stage. Unfortunately, the individual and/or cumulative delay required for each "carry ripple" between adjacent circuit stages leads to unacceptable transition speed.
This problem has previously been addressed in U.S. Pat. Nos. 3,943,478 and 4,679,216 which disclose a synchronous counter employing a method wherein a unit counter accumulatively gates output signals from one or more first circuit stages, and thereafter uses the gated signals as input signals to one or more subsequent circuit stages. The input portion of a NAND gate used in the gating operation of the foregoing synchronous counter is complicated. Yet, the NAND gate must also be very small physically depending on the number of stages in the counter. This conflict results in problems with the integration of the overall device.
Thus, it has proved difficult to address the problem of slow transition speed for the carry signal between adjacent circuit stages. Transition speed is an important operational parameter for synchronous counters responding to a synchronous clock. In particular, transition speed deficiencies in a synchronous counter used in semiconductor memory device, such as a DRAM, lead to malfunction of the overall memory device, and/or reduction in the reliability of the counter addressing operation.
A conventional counter is disclosed in Korean Patent Application No. 93-23598 entitled "A Synchronous Binary Counter" on Nov. 8, 1993. FIG. 1 shows a unit counter disclosed in the above patent application. FIG. 2 shows a multi-stage counter configured with a plurality of unit counters like the one shown in FIG. 1. FIG. 3 is a timing diagram for the conventional synchronous counter shown in FIG. 1.
In the conventional synchronous counter of FIG. 1, CLK is used as a reference indicator for a master clock signal. SET is an external signal used to designate an initial address for the counter. Ai is an interior address signal received from a buffer to which external address signals are applied. CAi is a counter output signal. "Carry i" indicates a carry signal from the conventional counter at a time i.
The operation of the conventional synchronous counter will be described hereinafter with reference to FIGS. 1 and 3. A typical operation cycle begins with SET changing from a logical "low" to "high" during the period in which CLK is high. The high SET signal is inverted by an inverter 6, again inverted by inverter 8, and these signals are respectively applied to transmission gate 10. See FIG. 3 between t1 and t2. As a result, transmission gate 10 is turned ON and a first latch circuit 14, controlled by ground isolation transistor 26 and control signal .phi.VCCH inverted by inverter 24, latches inverted address signal Ai. Further, the output of a NOR gate 4, node N1, is low because of the high clock signal CLK and the double inverted, high signal SET. The signal at node N1 is inverted by inverter 22. If node N1 becomes low, a transmission gate 12 is turned OFF, and a transmission gate 16 is turned ON. Thus, the output of first latch circuit 14 is applied to a second latch circuit 18 through transmission gate 16. Second latch circuit 18 latches the inverted output of first latch circuit 14 and generates signal CAi as an output.
In case where CLK and SET are low and a Carry (i-1) is high, the operation of the synchronous counter is as follows. When SET becomes low, transmission gate 10 is turned OFF and the input path of address signal Ai is closed. Since the high Carry (i-1) is applied to NOR gate 4 through inverter 2, all three inputs to NOR gate 4 are low, thus, making node N1 high. Transmission gate 12 is turned ON, and transmission gate 16 is turned OFF. Accordingly, first latch circuit 14 latches the inverted signal CAi output from an inverter 20 and input to first latch circuit 14 through transmission gate 12. At this time, first and second latch circuits 14 and 18 are isolated by the transmission gate 16.
Referring to time t3 in FIG. 3, if CLK again changes to high, node N1 again becomes low. Accordingly, transmission gate 12 is turned OFF and transmission gate 16 is turned ON. Second latch circuit 18 reversely latches CAi latched during the time interval between times t2 and t3 by the output of the first latch circuit 14. At time t3, CAi output by second latch circuit 18 is input to a carry generating logic gate in a subsequent circuit stage.
Referring now to FIG. 2, after NANDing CA0 and CA1, a carry 1 is generated by inverting the output of a NAND gate 31 with inverter 32. A carry 2 is generated by NORing CA2, inverted with inverter 33, and carry 1 in NOR gate 34. Further, after NANDing CA3 and carry 2 in a NAND gate 35, a carry 3 is generated by inverting the an output of NAND gate 35 with an inverter 36. In the same manner as the above, the other carry signals are generated in illustrated stages. In the case of an odd carry K, a carry CA(K) and a carry (K-1) are applied to a NAND gate and an inverter. In the case of an even carry L, the inverted values of a carry CA(L) and a carry (L-1) are applied to a NOR gate. In this manner, the carry propagation is performed by the logic gates of FIG. 2. Additionally in FIG. 2, a three-input NAND gate 39 receives signal line 45 to rapidly setting a carry 5 to low when the carry becomes low.
This configuration allows a normal count operation to be performed in the most significant bit counter with sufficient speed to allow system clock operation in a high frequency range of 150 MHz. However, where the address signal is set in the counter according to an external signal and the output signal generated in the counter is propagated to the carry generating logic gate after setting the interior of the counter, the carry generating time is delayed by the interval required to set the interior of the counter with the exterior address signal. As a result, conventional counters can not operate at frequencies sufficient to support evolving semiconductor applications.